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招聘公告详情
默升科技（上海）有限公司2022校园招聘简章
公司简介
CREDO【NasdaqListed CRDO】创立于2008年，是全球领先的半导体芯片设计公司，总部位于美国硅谷，目前在美国硅谷、中国上海设有全球研发中心，在香港、台湾、武汉、南京均设有分支机构。公司使命是，不断突破带宽壁垒，为数据基础设施市场中各种连接场景提供即速安全的信息传输解决方案。多年来致力于提供超高速单通道112G/56G/28G连接的商业解决方案，拥有业内最完善的SerDes产品组合，是全球屈指可数的，可在28nm/16nm/12nm/7nm/5nm全部工艺节点上实现400G/800G连接的商业解决方案的高科技半导体公司。CREDO目前拥有五大产品线，包括：SerDesChiplets; SerDesIP许可；光DSP芯片；Linecard芯片、HiWireAEC有源电缆。其中HiWireAEC是CREDO自主创新研发的线缆品类。产品满足全球客户对成本、功耗、性能等多方位的要求，被广泛服务于大型数据中心、云计算、5G、互联网，AI等前沿科技领域，享誉全球。
伴随着公司不断的技术进步和团队的飞速发展，CREDO在全球通讯行业的影响力不断提高： 作为行业技术领导者，CREDO参与IEEE,OIF行业联盟标准制定；也是OCP企业成员，并于2017和2019年连续两度获得台积电（TSMC）开放创新平台专业IP技术大奖。CREDO更是HiWire 
全球产业联盟发起人，如今已经有35家知名企业加入，共同致力于建立即插即用AEC在高速互联领域的行业标准，并持续推广这一更低能耗和更高速度的连接方式，以科技改变世界。
CREDO秉承“技术领先，以人为本”的经营理念，始终坚持技术革新，并关注个人发展，欢迎海内外各类人才加入，与公司共同成长。
HiWire 全球产业联盟是支持HiWire AEC（有源电缆）应用与发展的非营利组织，旨在促进高质量、可兼容的HiWire有源电缆AEC设备开发，建立HiWire AEC从研发、生产、测试到使用的行业技术标准及生态系统，提高公众认知并激发终端用户对HiWire AEC使用需求。
简历投递
简历投递邮箱：recruiting@credosemi.com
简历命名格式：姓名+意向城市+意向职位
公司官网
网申链接：
职位详情：
1. IC数字后端工程师Physical Design Engineer
职位描述：
1) 负责（28nm/16nm/7nm/5nm）芯片从门级网表到GDSII的物理实现及流程开发；包括布局规划，电源规划和分析，布局布线，静态时序分析，物理验证及其签核；
2) 负责IP核的物理集成及验证；
3) 与其他团队协作，优化设计，以实现设计收敛；
4) 直线经理安排的其他任务。
Responsibilities:
1. Responsible for the physical design and process development from gate-level netlist to GDSII; Including floor planning, power planning, place and route, timing closure, static timing analysis and physical verification and signoff.
2. Responsible for IP physical integration and verification.
3. Responsible for interaction with the front-end design team to realize the design convergence and optimization of the front and back ends.
4. Other tasks your line manager assigned you.
任职要求：
1) 微电子、集成电路、物理和材料相关专业本科及以上学历的应届毕业生；
2) 理解能力和表达能力优秀；
3) 拥有硕士学位或者相关工作经验者较优；
4) 具有良好的沟通能力和团队合作精神。
Requirements:
1. A bachelor's degree is essential and major in microelectronics, integrated circuit, physics or material.
2. Ability to understand and articulate technical issues.
3. An MS degree and/or working experience is a plus.
4. Self-motivated with good communication skills and team spirit.
招聘人数： 2人
Headcount in demand：2
工作地点：南京
Location：Nanjing
投递链接：
https://www.myjob500.com/JobSearch/JobDetails?JobId=689bf50b-d868-4f96-bba1-d9ced5015ae3
2. 可测性工程师DFT（Design for Test）Engineer
职位描述：
1) 负责DFT电路(包括scan 、memory BIST和Boundary Scan)的规划，设计和集成；
2) 负责DFT部分的RTL和门级网表的仿真验证工作；
3) 负责DFT ATE测试向量的生成，并协助机台测试工程师完成debug；
4) 负责建立和维护DFT设计验证自动化流程；
5) 负责设计的综合，静态时序分析和形式验证工作。
Responsibilities:
1. Responsible for the planning, design and integration of DFT circuits (including scan, memory BIST and boundary scan.
2. Responsible for the simulation of DFT design at RTL and gate level.
3. Responsible for the generation of DFT test vectors for CP and ATE test, and assist the ATE engineer to debug.
4. Establish and maintain DFT design and verification automation flow.
5. Responsible for synthesis, static timing analysis and formal verification of DFT mode.
任职要求：
1) 集成电路，微电子，光电，通信等专业本科及以上学历的应届毕业生；
2) 具有扎实的数字电路基础知识；
3) 熟悉硬件描述语言Verilog或VHDL；熟悉python，tcl，perl等脚本语言；
4) 有较强的英语沟通能力、自主学习能力、沟通能力和团队合作能力；
5) 熟悉ASIC设计流程，有EDA工具使用经验者优先。
Requirements:
1. Bachelor degree or above in integrated circuit, microelectronics, optoelectronics, communications, etc.
2. Solid basic knowledge of digital circuit.
3. Familiar with hardware description language Verilog or VHDL; Familiar with python, tcl, perl and other scripting languages.
4. Strong English communication ability, self-study ability, communication ability and teamwork ability.
5. Familiar with ASIC design flow, experience in using EDA tools is preferred.
招聘人数： 5人
Headcount in demand：5
工作地点：武汉
Location：Wuhan
投递链接：
https://www.myjob500.com/JobSearch/JobDetails?JobId=689bf50b-d868-4f96-bba1-d9ced5015ae3
3. 数字集成电路设计/验证工程师ASIC Design/Verification Engineer
职位描述：
1) 参与芯片级和模块级架构定义；
2) 使用Verilog/SV语言实进行RTL设计工作；
3) 进行数字集成电路RTL与网表的仿真、验证工作；
4) 参与综合以及时序收敛工作；
5) 与其他设计团队紧密合作，完成芯片流片工作。
Responsibilities:
1. chip level and module level architecture definition.
2. RTL design using Verilog/SV.
3. RTL/netlist simulation.
4. synthesis and timing closure.
5. Co-work with other teams .
任职要求：
1) 集成电路，微电子，光电，通信等专业本科及以上学历的应届毕业生；
2) 具有良好的数字电路基础，熟悉硬件描述语言Verilog/System Verilog；
3) 熟练使用各种相关EDA工具，熟悉IC设计流程；
4) 熟悉TCL/Shell/Perl/Python编程；
5) 具有较强的学习能力与独立分析、解决问题的能力，以及良好的团队合作精神；
6) 英语流利，善于沟通。
Requirements:
1. Bachelor degree or above in integrated circuit, microelectronics, optoelectronics, communications, etc.
2. Good background of digital circuit, familiar with verilog/SV.
3. Good experience in EDA tools, familiar with IC design flow.
4. Familiar with TCL/Shell/Perl/Python.
5. Strong learning capability, can solve problems independently,good team-worker.
6. Good capability in Written and Spoken English .
招聘人数：5人
Headcount in demand：5
工作地点：武汉/上海
Location：Wuhan/Shanghai
投递链接：
https://www.myjob500.com/JobSearch/JobDetails?JobId=689bf50b-d868-4f96-bba1-d9ced5015ae3
4. 芯片系统设计工程师Digital SOC Design Engineer
职位描述：
1) 负责芯片数字模块设计与功能验证；
2) 负责前端flow的工作，包括sdc编写和调试，综合、形式验证、时序检查等工作；
3) 负责SoC系统或子系统集成；
4) 对芯片对应模块测试和调试提供技术支持。
Responsibilities:
1. Responsible for chip digital module design and function verification.
2. Responsible for front-end flow work, including sdc writing and debugging, synthesis, formal verification, timing check, etc.
3. Responsible for SoC system or subsystem integration.
4. Provide technical support for the testing and debugging of chip corresponding modules.
任职要求：
1) 集成电路，微电子，光电，通信等专业本科及以上学历的应届毕业生；
2) 熟悉IC设计流程，掌握前端EDA工具；
3) 会使用Verilog或VHDL进行开发；
4) 掌握亚稳态，竞争冒险和时序等数字电路基础知识；
5) 一定的英文能力和团队协作能力。
具备以下能力优先：
1) 熟悉RISCV MCU以及wishbone/apb/ahb/axi总线优先；
2) 熟悉UART/SPI/I2C/MDIO等常用外设接口优先；
3) 有FPGA和MCU使用经验优先，有流片经验优先；
4) 掌握c语言或csh，perl，python等脚本语言优先。
Requirements:
1. Fresh graduates with bachelor degree or above in integrated circuits, microelectronics, optoelectronics, communications and other related majors.
2. Familiar with IC design process and master front-end EDA tools.
3. Will use Verilog or VHDL for development.
4. Master the basic knowledge of digital circuits such as metastability, competitive adventure and timing.
5. Certain English ability and teamwork ability.
The following abilities are preferred:
1. Familiar with RISCV MCU and wishbone/apb/ahb/axi bus is preferred.
2. Familiar with common peripheral interfaces such as UART/SPI/I2C/MDIO is preferred.
3. Experience in using FPGA and MCU is preferred, and experience in tape-out is preferred.
4. Knowledge of c language or scripting languages such as csh, perl, python is preferred.
招聘人数：5人
Headcount in demand：5
工作地点：武汉/上海
Location：Wuhan/Shanghai
投递链接：
https://www.myjob500.com/JobSearch/JobDetails?JobId=689bf50b-d868-4f96-bba1-d9ced5015ae3
5. 项目工程师Digital Project engineer
职位描述：
1) 负责部门经理下达的项目运作、跟踪与落实，控制并确保必要的研发步骤；
2) 负责项目各阶段工作的推进和问题的处理；
3) 能胜任新产品有关文件的编制，并对文件的准确性、完整性负责；
4) 配合其他部门对客户的技术服务支持工作；完成上级领导交待的其他工作。
Responsibilities:
1. Follow up project plan and make projects complete on time.
2. Work with other functional department to guarantee the project success.
3. Work with team to prepare necessary internal and external project documentation.
4. Responsible for all documentation archiving and transfer.
5. Do all other duties as assigned.
任职要求：
1) 集成电路，微电子，光电，通信，计算机等相关专业本科及以上学历的应届毕业生；
2) 具有电子电路和晶体管之理论基础，掌握 IC设计流程、方法及工具，熟悉集成电路制造过程及工艺；
3) 熟悉Perl/Python编程；
4) 良好的英语听、说、读、写能力，能熟练阅读英文资料并能撰写技术规范，设计和测试报告；
5) 优秀的数据分析能力和清晰严谨的思路；
6) 具备良好的沟通协调能力和团队协同意识，协助项目过程推动，整合项目资源与产品优化。
Requirements:
1. Bachelor degree or higher, electronic engineering and computer science related majors are preferred.
2. Have a basic knowledge in all stages of the ASIC design flow (including specification, architecture, and design implementation.
3. Good English communication and report writing skill.
4. Good data analysis skill.
5. Highly organized and self-motivated.
6. Good team work spirit and able to work with diverse team members in China and overseas.
招聘人数：5人
Headcount in demand：5
工作地点：武汉/上海
Location：Wuhan/Shanghai
投递链接：
https://www.myjob500.com/JobSearch/JobDetails?JobId=689bf50b-d868-4f96-bba1-d9ced5015ae3
6. 数字后端设计工程师Physical Design Engineer
职位描述：
1) 负责SoC芯片(28nm、16nm、7nm)的物理实现流程开发；
2) 完成芯片顶层从门级网表到GDS的实现，包括布图规划、布局布线、时序分析、功耗分析、物理验证等；
3) 解决模块级物理设计方面的问题。
Responsibilities:
1. Responsible for the physical implementation process development of SoC chips (28nm, 16nm, 7nm).
2. Complete the physical design and process development from gate-level netlist to GDS; Including floor planning, power planning, place and route, timing closure, static timing analysis and physical verification and signoff.
3. Solve the problem of module-level physical design.
1) 全日制电子类集成电路及光电通信专业学士以上学历、硕士尤佳；
2) 学习成绩优秀，对新生事物及专业相关领域知识具有极强的学习能力和知识迁移能力；
3) 希望未来往IC后端工程师方向发展；
4) 了解超大规模集成电路物理设计的基本概念和知识。
加分（非必备）项 ：
5) 具有脚本开发能力，使用过Tcl、Perl等脚本语言；
6) 具备芯片数字后端设计经验；
7) 有获奖经历/有学生干部经验/优秀毕业生/获优秀毕业论文。
Requirements:
1. Bachelor degree or above in electronic integrated circuit and photoelectric communication, master degree is preferred.
2. Excellent academic performance, strong learning ability and knowledge transfer ability for new things and related fields.
3. Hope to develop into physical design engineer.
4. Understand the basic concepts and knowledge of VLSI physical design.
The following abilities are preferred:
1. Script development ability, using Tcl, Perl and other script languages.
2. Experience in physical design engineer.
3. Award winning experience/student cadre experience/Outstanding graduate/outstanding graduation thesis.
招聘人数：5人
Headcount in demand：5
工作地点：武汉/上海
Location：Wuhan/Shanghai
投递链接：
https://www.myjob500.com/JobSearch/JobDetails?JobId=689bf50b-d868-4f96-bba1-d9ced5015ae3
7. 产品工程师（Product Engineer）
职位描述：
1) 与Credo工程团队合作，在AEC（有源电缆）生产测试环境中开发测试工具、测试站、测试夹具、测试计划和方法；
2) 新产品导入中的测试性可行性研究，着重解决量产阶段的关键测试相关问题；
3) 为内部团队在产品失效分析方面提供支持，通过DOE推动问题解决，并支持提高产品良率和降低成本；
4) 电气工程至电路级的全方位工作知识，理解并领导团队解决问题；
5) 掌握测试仪开发中使用的软件工程技能以及复杂模块中使用的固件；
6) 在向制造供应商发布测试软件之前，推动运营和工程团队解决潜在测试问题和故障相关性问题；
7) 解决测试问题，提高测试覆盖率，并为制造供应商制定相关测试规格。
Responsibilities:
1. Work with Credo Engineering teams to develop test tools, test stations, test fixtures, test plans and methodologies in AEC (Active Electrical Cable) production-testing environment.
2. Testability study in NPI and emphasize on resolving critical test related issue in mass production phases.
3. Provide support to internal team in product failure analysis, drive issue resolutions via DoEs and support production yield improvement and cost down activities.
4. All-rounder working knowledge of electrical engineering down to circuit level to understand and lead team in solving issues.
5. Master in software engineering skills used in tester development as well as firmware used in complex modules.
6. Drive closure on potential test gap & failure correlations between OPS and Engineering Team before Release to CMs.
7. Closing test gaps, improving test coverage and mapping out margins at CMs.
任职要求：
1) 电子信息工程/通信工程/软件工程的学士/硕士学位；
2) 与内部跨职能团队和外部 CM 合作伙伴合作的沟通能力强；
3) 可以经常出差到全球包括中国以外的CM站点；
4) 良好的英语，书面和口头表达能力；
5) 良好的数据分析软件技能包括python、C、其他
Requirements:
1. BS/MS in Electronic and Information Engineering /telecom engineering / Software Engineering.
2. Strong communication skills to work with internal cross-functional teams and external CM partners.
3. Can frequent business travel to CM sites globally including out of China.
4. Good command of English, written and oral.
5. Good data analysis software skill include python, C, others
招聘人数：2人
Headcount in demand：2
工作地点：上海
Location： Shanghai
投递链接：
https://www.myjob500.com/JobSearch/JobDetails?JobId=689bf50b-d868-4f96-bba1-d9ced5015ae3
8. ATE测试工程师ATE Testing Engineer
职位描述：
1) 与 IC 设计团队和 DFT团队 ,SE团队沟通制定测试方案；
2) 根据芯片测试方案完成 Loadboard，Socket，Probe card，changekit 等 ATE 测试硬件的委外设计加工；
3) 负责 CP/FT 测试程序开发。包括测试程序编写、调试、发布和版本管理; 保证测试程序稳定性, 提高测试覆盖率，提升良率、优化测试时间；
4) 负责工程样品，可靠性样品，封装可靠性样品，老化样品，早夭样品，客诉样品，工程批样品等的测试，帮助产品工程师收集、分析测试数据；
5) 负责项目各阶段的测试验证工作，确保量产的顺利导入；
6) 支持产品工程师完成测试良率异常分析工作。
Responsibilities:
1. Communicate with the IC design team, DFT team, and SE team to formulate test plans.
2. Complete the outsourcing design and processing of Loadboard, Socket, Probe card, changekit and other ATE test hardware according to the chip test plan.
3. Responsible for CP/FT test program development. Including test program writing, debugging, release and version management; to ensure the stability of test programs, test coverage, yield improvement, and test time optimization.
4. Responsible for the testing of engineering samples, reliability samples, package qual samples, HTOL samples, ELFR samples, RMA samples, engineering lot, etc., and help product engineer collect and analyze test data.
5. .Responsible for the testing and verification of each stage of the project to ensure the smoothly release to mass production.
6. Support PE to complete the abnormal analysis of low yield.
任职要求：
1) 电子工程相关专业本科及以上学历；
2) 精通使用至少一种计算机编程语言（如 C，C++，Python，Java等）；
3) 具备良好的沟通、协调能力及团队合作意识。
Requirements:
1. Bachelor degree or above in electronic engineering related majors.
2. Proficient in using at least one computer programming language (such as C, C++, Python, Java, etc.).
3. Have good communication, coordination skills and teamwork awareness.
招聘人数：1人
Headcount in demand：1
工作地点：上海
Location：Shanghai
投递链接：
https://www.myjob500.com/JobSearch/JobDetails?JobId=689bf50b-d868-4f96-bba1-d9ced5015ae3
9. 产品工程师Product Engineer（System Level Testing）
职位描述：
1) 与芯片设计和应用工程师合作，确定集成电路芯片的SLT测试计划；
2) 与硬件工程师合作，开发SLT硬件方案；
3) 与应用工程师合作，编写、调试并验证基于python的SLT测试脚本；
4) 完成实验批次的集成电路芯片的SLT测试；
5) 将 SLT HW 和 SW 导入到 fab 以进行大规模生产，并且对其进行维护；
6) 与芯片设计和应用工程师共同合作，分析集成电路芯片的电气功能故障；
7) 使用大数据方法，收集并分析 SLT 测试数据，以便优化测试覆盖率，降低成本，提高良率。
Responsibilities:
1. Work with designer and application engineer to confirm IC chip’s SLT test plan.
2. Work with hardware engineer to develop SLT hardware solution.
3. Work with application engineer to code, debug and validate SLT test script based on python.
4. Complete SLT test validation in the pilot lot of IC chips.
5. Transfer SLT HW and SW to fab for mass production run and maintain them.
6. Co-work with designer and application engineer to analyze IC chip’s electrical function failure.
7. Use big data methods collect and analyze SLT test data to optimize test coverage, reduce cost and improve yield.
任职要求：
1) 需要了解半导体基本原理；
2) 需要了解数字和模拟电路的基本原理；
3) 需要精通一种或多种编程语言（Perl/Python/C/C++/Java/C#）；
4) 需要良好的英语口语和书写能力；
5) 具有良好的人际沟通能力，学习能力强，强大的自我驱动；
6) 了解测试原理和测试方法；
7) 熟悉硬件电路调试；
8) 熟悉基本数据统计技能优先；
9) 熟悉传输通信、Serdes 或光学优先；
10) 有集成电路芯片测试经验优先。
Requirements:
1. Know about Semiconductor basic principles is required.
2. Know about digital and analog circuit basic principles is required.
3. Good in one or more of programing languages (Perl/Python/C/C++/Java/C#) is required.
4. Good spoken and written English is required.
5. Good communication skill with people, strong learning ability and powerful self-driving is required.
6. Know about test principles and test methodology.
7. Familiar with hardware circuit debug.
8. It is a plus to be familiar with Fundamental data statistics skill.
9. It is a plus to be familiar with transmit communication, Serdes, or Optical.
10. It is a plus to have the experience with IC chips testing.
招聘人数：2人
Headcount in demand：2
工作地点：上海
Location：Shanghai
投递链接：
https://www.myjob500.com/JobSearch/JobDetails?JobId=689bf50b-d868-4f96-bba1-d9ced5015ae3
10. 产品工程师Product Engineer（For IC）
职位描述：
1) 关注产品的可测试性；提供产品电气故障分析、数据统计、成品率改进和ATE测试程序内部验证，负责ATE测试程序的签署和发布，并移交给OSAT；
2) 拥有测试线产量监视器（go或no go命令）和测试规范，不断优化产量改进；
3) 与设计团队一起参与验证测试开发，重点是第一个硅原型样品，特别是与铸造工程师合作，提供ATE测试数据和fab WAT数据之间的相关性分析。
Responsibilities:
1. Focus on the testability of product; provide product electrical failure analysis, data statistics, yield improvement, and ATE testing program in-house validation, take charge of ATE testing program sign off and release, as well transfer to OSATs.
2. Own the testing line yield monitor(go or no go command) and test spec continuously optimization for yield improvement.
3. Participate the validation tests development with design team with emphasis on 1st silicon prototype sample, especially co-work with Foundry Engineer providing the correlation analysis between ATE testing data and fab WAT data.
任职要求：
1) 本科学历及以上，电子、电气、微电子、应用数理统计或计算机工程专业；
2) 良好的英语听说读写能力；
3) 渴望学习，良好的人际关系和沟通能力；
4) 测试工程师或具有测试工程背景，尤其是V93K测试仪家族背景者优先；
5) 用于统计数据分析的JMP或Minitab；
6) 电路设计知识，尤其是模拟电路设计（PLL、ADC、DAC），具备基本的高速SerDes电路设计知识者优先；
7) 能够在压力下工作，自我激励能力强。
Requirements:
1. Bachelor's or above, Electronics, Electrical, Microelectronics, Applied Mathematic & Statistics or Computer Engineering.
2. Good command of written and spoken English.
3. Eager to learn, good interpersonal and communication skill.
4. Testing Engineer or of having testing engineering background especially family with V93K tester is a good plus.
5. JMP or Minitab for statistical data analysis.
6. Knowledge of circuit design especially on analog circuit design (PLL, ADC, DAC), basic high speed SerDes circuit design knowledge would be an added advantage.
7. Ability to work under pressure, strong self-motivation.
招聘人数：2人
Headcount in demand：2
工作地点：上海
Location：Shanghai
投递链接：
https://www.myjob500.com/JobSearch/JobDetails?JobId=689bf50b-d868-4f96-bba1-d9ced5015ae3
11. 芯片验证工程师Digital Verification Engineer
职位描述:
1) 根据spec分析测试条件，编写测试文档，设计测试case；
2) 搭建验证平台，编写验证用例，执行验证；
3) Failure、Bug 分析及定位，Coverage 分析，merge及收敛；
4) 配合数字（前端与后端）设计师，进行数字前仿与后仿。
Responsibilities:
1. Analyze test conditions according to spec, write test documents, and design test cases.
2. Build a verification platform, write verification cases, and execute verification.
3. Failure, Bug analysis and positioning, Coverage analysis, merge and convergence.
4. Cooperate with digital (front-end and back-end) designers to carry out digital pre- and post-simulation.
任职要求：
1) 本科及以上学历，微电子、电子工程、电子信息工程或相关专业；
2) 熟悉linux环境，熟练掌握Verilog，system-verilog等语言；
3) 熟悉uvm，能够独立建立uvm测试平台；
4) 熟悉irun/vcs、Verdi，vmanager等eda工具；
5) 具有较强的学习能力、分析能力、沟通能力和团队合作精神；
具备以下能力优先：
1) 熟练编写perl、csh、tcl等脚本；
2) 熟悉FPGA验证平台，能够配合进行FPGA验证；
3) 熟悉C/C++等编程语言，熟悉 reference model 的开发及使用；
4) 有参与成功流片经验优先。
Requirements:
1. Bachelor degree or above, major in microelectronics, electronic engineering, electronic information engineering or related.
2. Familiar with Linux environment, proficient in Verilog, system verilog and other languages.
3. Be familiar with uvm, and be able to build a uvm test platform independently.
4. Familiar with irun/vcs, Verdi, vmmanager and other eda tools.
5. Strong learning ability, analytical ability, communication ability and team spirit.
The following abilities are preferred:
1. Proficiency in writing perl, csh, tcl and other scripts.
2. Familiar with FPGA verification platform, able to cooperate with FPGA verification.
3. Familiar with C/C++ and other programming languages, familiar with the development and use of reference models.
4. Experience in participating in successful tapeout is preferred.
招聘人数：2人
Headcount in demand：2
工作地点：武汉/上海
Location：Wuhan/Shanghai
投递链接：
https://www.myjob500.com/JobSearch/JobDetails?JobId=689bf50b-d868-4f96-bba1-d9ced5015ae3
